1. Field of the Invention
The present invention relates to a digital signal processing method and a digital signal processing device for use in a digital signal reproduction apparatus such as a digital video tape recorder (VTR), and in particular to a signal processing method and a signal processing device for restoring original association relations between channels of reproduced signals and channels of a signal processing circuit which have been interchanged in case the tape speed in reproduction operation is different from that in recording operation when data divided into a plurality of channels and recorded on the tape are to be reproduced.
In a conventional digital signal reproduction apparatus such as a conventional digital VTR, digital signals are distributed into a plurality of channels and are recorded as a plurality of magnetic tracks by a plurality of rotary magnetic heads.
When data thus divided into a plurality of channels and recorded onto the tape are to be recorded and a special reproduction mode such as a variable speed reproduction mode (in which data are reproduced at a tape speed different from the tape speed of the recording operation) other than a normal reproduction mode (in which data are reproduced at the same tape speed as that of the recording operation) is used, the association relations between channels of signals reproduced by a reproduction head and channels of the reproduced signal processing circuit connected to the reproduction head are interchanged. In U.S. Pat. No. 4,392,162, for example, therefore, original association relations are restored by a switch circuit referred to as data interchanger as shown in FIG. 1.
FIG. 1 is a block diagram showing the configuration of the reproduction side shown in the above described U.S. Patent. In FIGS. 1, 1A, 1B and 1C denote reproduction heads for reproducing signals of channels A, B and C respectively recorded on tracks A, B and C, respectively. Further, 30A, 30B and 30C denote reproduction amplifiers, 31A, 31B and 31C reproduction processors, 32A, 32B and 32C time base collectors (TBC), 33 a data interchanger, 34A, 34B and 34C error correction decoders, 35A, 35B and 35C time base expansion circuits, 36 an interface, 37 a D-A converter, 38 an output processor, and 39 an output terminal.
FIG. 2 schematically shows the interchanger 33 and channel memories 4A, 4B and 4C respectively included in the decoders 35A, 35B and 35C of the above described U.S. Patent. The interchanger 33 includes three interchanger circuits (switch circuits) 33A, 33B and 33C respectively supplied with 3-channel input signals 1a, 1b and 1c respectively from TBC's 32A, 32B and 32C.
The 3-channel input signals 1a, 1b and 1c are respectively selected by the interchanger circuits 33A, 33B and 33C, and supplied to respective channel memories 4A, 4B and 4C assigned beforehand as write-in signals 11a, 11b and 11c, respectively. These signals 11a to 11c are written into respective channel memories 4A to 4C and are read out as output signals 7a to 7c when data corresponding to one frame are stored into the memories. The output signals 7a to 7c then undergo error correction.
As described above, the interchanger circuit aims at restoring the original association relations because channels of reproduced signals in the variable speed reproduction mode and channels of the reproducing signal processing circuit are interchanged. At a particular tape speed, however, the processing for restoring the original association relations becomes impossible as described later.
FIG. 3 shows a pattern (reproduced signals) read out by the heads 1A to 1C when signals recorded on a tape 20 by heads disposed at intervals of 120.degree. on the periphery of a drum of a VTR are reproduced at a tape speed which is three times as fast as that of normal reproduction mode.
Signals of the channel A are recorded on tracks A, A', A", A"' and so on. Signals of the channel B are recorded on tracks B, B', B", B"', and so on. And signals of the channel C are recorded on tracks C, C', C", C"' and so on.
Signals of the tracks A, B, C, A', B', C', A" and so on are reproduced in this order by the head 1A. At this time, signals of the tracks A', B', C', A", B", C", A"' and so on are reproduced by the head 1B in the same way. Signals of the tracks A", B", C", A"', B"', C"' and so on are reproduced by the head 1C.
The first track reproduced by the head 1B is the track A' because the tape speed is three times as fast as that of the normal reproduction mode and the tape moves at a speed which is three times as fast as that of the normal reproduction mode although the time taken for the drum to rotate by 120.degree. is constant. In this case, signal processing becomes very difficult. The reason will now be described. Signals of the same channel are simultaneously reproduced by the heads 1A to 1C. For example, the channel A is reproduced by the heads 1B and 1C as well when the channel A is reproduced by the head 1A. However, only one memory A is present in FIG. 2. Therefore, the interchanger circuit 33A does not know which of the signals 1a to 1c should be written into the memory A. Accordingly, only one third of information is written into the memory A, and the remaining two-thirds of information is discarded.
As a result, the reproduced pictorial image becomes very unnatural.